1. Field of the Invention
This invention relates to a semiconductor integrated circuit and method of inter-layer connection therefor, using a contact having a relatively longer lengthwise dimension than a widthwise dimension for electrically connecting different layers to each other, which are a plurality of layers of laminated structure such as wiring layers made of polycrystalline silicon and metal, and more particularly to a semiconductor integrated circuit and method of inter-layer connection therefor, in which electric resistance by the contact is decreased.
2. Description of the Prior Art
In recent years, the degree of integration of the semiconductor integrated circuit has been further improved, and, along with this tendency, the dimensions of a contact for electrically connecting different layers to each other within the semiconductor integrated circuit have been further decreased.
However, with the above-described contact having small dimensions, such a problem is presented that it is difficult to work on it with high accuracy.
For example, with an elongate contact, the turn-in amount of light at the time of exposure is increased, and saggings of a photoresist at the time of developing or baking are different depending on the longer side or the shorter side of the contact, thus presenting such a problem that the widths of the contacts become uneven. For example, when a positive photoresist is used, the contact width at the central portion of the elongate contact is widened. When the width at the central portion of the contact is widened as described above, such a problem is presented that a portion, which should not be etched, is etched during etching.
In Japanese Patent Publication No. 33746/1987, contacts in an elongate contact region are formed of a plurality of square contacts spaced apart from one another, so that the working accuracy of the contact in the elongate contact region of this type can be improved.
FIG. 11 is an integrated circuit pattern diagram showing the semiconductor integrated circuit in which the conventional contacts are used.
In the integrated circuit pattern shown in this FIG. 11, a NAND logic gate shown in the circuit diagram in FIG. 12 is constituted by the contacts disclosed in the aforesaid Japanese Patent Publication No. 33746/1987.
That is, in this FIG. 11, the contacts formed by the plurality of square contacts spaced apart from one another are used for connection between a power line VDD and source of a P channel MOS transistors TP1 and TP2, connection between a drain of the P channel MOS transistor TP1, a drain of the P channel MOS transistor TP2 and a drain of an N channel MOS transistor TN1 and connection between a source of an N channel MOS transistors TN2 and a ground line GND.
Even when the dimensions of the integrated circuit pattern of the logic gate such as the NAND logic gate are reduced to improve the degree of integration of the semiconductor integrated circuit, by applying the technique disclosed in Japanese Patent Publication No. 33746/1987 as described above, the working accuracy of the contacts used in this semiconductor integrated circuit can be improved.
However, when the contacts disclosed in the aforesaid Japanese Patent Publication No. 33746/1987 are used, such a problem is presented that portions between the plurality of contacts in the integrated circuit pattern cannot be used for electrical connection, whereby the area of the contact region where the contacts can be arranged cannot be effectively used. Therefore the electric resistance by the contacts is increased, so that electrical properties are deteriorated.
More specifically, in FIG. 11, when supplied from the power line VDD or the ground line GND, an output current outputted from an output terminal Y flows through predetermined contacts. In this case, when the electric resistance of the respective contacts are increased, the output properties and the like of the logic gate is deteriorated.